Electronic data processing systems have evolved from large, cumbersome devices using vacuum tubes to compact and inexpensive microprocessor based devices utilizing large scale integrated circuitry. In recent years, much effort has been placed upon increasing the flexibility of the computer system while at the same time minimizing its costs. It has been recognized that this criteria can be met by using a modular approach in which the capabilities of the data processing system can be expanded or changed merely by adding new circuit boards which contain circuitry for performing different functions. Intel Corporation's MULTIBUS system is illustrative of this approach. It contains a single system bus through which each functional module communicates with each other. In general, the system includes a central processing unit (CPU) on one circuit board and a plurality of different slave modules which interface with different peripheral units such as displays, printers, etc.
One of the problems associated with this modular technique is that it is extremely important for the CPU, which is located on one circuit board, to keep track of the operational status of the slave modules which are on other circuit boards. In the Intel MULTIBUS system, when the CPU wants the slave module to perform an operation, it places the address of the slave module on the system bus. The slave module must respond to the CPU within an extremely short period of time to indicate to the CPU that the slave module is not capable of performing any further operations at that time. In particular, the slave module must indicate this "Not Ready" condition within about 50 nanoseconds. In order to maintain this rigid timing requirement, high cost components must be used. Moreover, these high speed devices utilize a substantial amount of power thereby further increasing system costs. In addition to these disadvantages, the prior art approach has difficulty in ascertaining "off board" error conditions. This is because the CPU assumes that the operation was completed by the slave module if it did not receive the "Not Ready" signal from the slave module within the allotted time. Consequently, if the slave module interconnection to the system bus is malfunctioning or if the slave module is not plugged into the system at all, the CPU will assume that the operation was complete and proceed to perform other tasks. This, of course, leads to improper system operation.